1. Field of the Invention
The present invention relates to a verification apparatus of a mask in a lithography process used in semiconductor fabrication, and more particularly, to a mask pattern verification apparatus employing super-resolution technique, a mask pattern verification method thereof, and a medium in which a program thereof is recorded.
2. Description of the Background Art
As semiconductor integrated circuit devices are scaled to higher densities, the necessity of microminiaturization of the pattern formed on a mask has become higher. However, there is limitation in the improvement of the resolution in microminiaturization. The super-resolution technique is now used in addition to the method of reducing the wavelength of the light source to effect microminiaturization. For example, the Levenson method and the modified illumination method are known such super-resolution technique.
In the Levenson method, the resolution of the pattern formed on a mask is improved for microminiaturization by arranging a phase shifter on the mask. In the modified illumination method, the resolution of the pattern formed on the mask is improved for microminiaturization by altering the configuration of the light source per se. The usage of the super-resolution technique allows a finer pattern to be formed on the mask.
In these few years, optical simulation has been employed for the purpose of estimating the final configuration of a pattern formed on a mask. FIG. 1 is a flow chart for describing the procedure of correcting a layout employed in conventional optical simulation. First, layout data is produced from the semiconductor circuit data generated by the circuit design (S101). In producing the layout data, the line width and the space width (exposure dimension) are prevented from taking a value smaller than a predetermined value. Then, mask data for use with optical simulation is generated from the produced layout data. Optical simulation is performed according to a predetermined optical condition (S102). By this optical simulation, the pattern that will be actually formed on a mask can be evaluated.
The user verifies the layout by referring to the result of the optical simulation (S103). For example, the user visually verifies the final configuration displayed on a screen. When the final configuration of the displayed pattern is not appropriate, the layout is corrected (S104), and the process from the optical simulation (S102) onward is repeated. After eliminating any defect in the final configuration of the pattern, a mask is formed.
As an alternative to the manual verification of step S103, the layout data can be corrected automatically employing OPC (Optical Proximity Correction) shown in FIGS. 2A and 2B. At the corner of a pattern, there is an area that cannot be irradiated sufficiently with the light. OPC is directed to approximate the final configuration to the desired configuration by expanding the area of the layout pattern that is not subjected to sufficient light, as shown in FIGS. 2A and 2B.
In correcting the layout employing the conventional optical simulation, the range that can be verified visually is limited. There was a problem that the verification of the entire layout was extremely time-consuming.
Furthermore, in the event of correcting the layout pattern by OPC, it was necessary to visually check whether the corrected result is proper or not. In other words, the layout subjected to OPC must be subjected to optical simulation again in order to verify the layout after the OPC shown in FIGS. 2A and 2B. The result of the optical simulation had to be verified again visually.
In the conventional layout verification system, it is difficult to correct the layout since it does not accommodate the super-resolution technique. Although the line width and the space width can be reduced than the level allowed according to the conventional resolution limit by employing the super-resolution technique, there is a phenomenon where the final line or space becomes larger or smaller at a certain dimension region. It was difficult to identify that certain dimension region and provide a process compensating for this phenomenon. It was difficult to estimate the final configuration of a mask pattern.